Micross

Abstract Preview

Here is the abstract you requested from the IMAPS_2009 technical program page. This is the original abstract submitted by the author. Any changes to the technical content of the final manuscript published by IMAPS or the presentation that is given during the event is done by the author, not IMAPS.

Near Chip Scale Package for High Power, Big Chip LEDs
Keywords: LED, CSP, flipchip
High power LEDs are rapidly evolving into devices that progressively bear less and less resemblance to the LEDs that we used to know. Todays LEDs feature higher brightness levels, higher operating power levels, larger die/emitter sizes, a shift from edge emission to surface emission, enhanced extraction and collimation of light, and increased efficacies. These changes are enabling applications that until now have been dominated by mercury-arc, high intensity discharge, halogen, incandescent and fluorescent bulbs, and previously were beyond the capability of LEDs. Now that LEDs can compete in many high brightness applications previously occupied by more traditional forms of lighting, new innovative forms of LED packaging are required. Handling high-density thermal dissipation, high optical power levels, tight mechanical tolerances and high current electrical interconnects now require packaging approaches that were previously unconventional, even unheard of, for LEDs. In order to address these new LED package requirements, a near-chip-scale package has been developed which bears little resemblance to traditional LED packages. This new packaging platform has borrowed from, and built on, a mix of packaging technologies more commonly associated with WLP, CSP, BGA, Memory ICs, RFICs, flip-chip and MEMS devices. This paper presents the challenges encountered, and solutions implemented, during design of the package and the associated process development. The package structural, thermal, optical and electrical design inputs are presented as well as the subsequent design approaches, including materials selection, prioritizing risks by DFMEA, and designing for manufacturability and reliability. The resultant package is a revolutionary, very compact, surface mount device which features a junction-to-case thermal resistance of <0.5 degrees C/W, zero optical loss/100% transmission, good optical interfacing due to elimination of wirebonds and their associated loop heights, excellent compatibility with state-of-the-art assembly manufacturing lines, and design flexibility including potential for MCM and SiP integration.
Paul Panaccione, Director Package Technology
Luminus Devices, Inc.
Billerica, MA


CORPORATE PREMIER MEMBERS
  • Amkor
  • ASE
  • Canon
  • EMD Performance Materials
  • Honeywell
  • Indium
  • Kester
  • Kyocera America
  • Master Bond
  • Micro Systems Technologies
  • MRSI
  • NGK NTK
  • Palomar
  • Plexus
  • Promex
  • Qualcomm
  • Quik-Pak
  • Raytheon
  • Specialty Coating Systems