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Parallel Algorithms for Power and Signal Integrity Analysis of High-Speed Designs
Keywords: Power Integrity, Signal Integrity, Parallel Algorithms
The ever increasing demand for higher data rates, lower power and multi-function capable products are necessitating newer generations of complex and denser electronic circuits and systems. With the advancing signal-speeds and decreasing feature sizes, high-frequency effects become the dominant factors limiting the overall performance of microelectronic systems. Also the desire for multifunction and miniature products warrant mixed-domain integration of heterogeneous circuit components such as digital, analog, RF, optical and micro-electro-mechanical (MEMS) devices. These issues coupled with the lower power requirement are making the modeling, analysis and design of power distribution networks (PDNs) consisting of chip, package and printed circuit boards, extremely challenging. This is because, the power grid network for integrated circuits can consist of millions of circuit elements, leading to computationally expensive and time consuming transient simulations. In this paper, novel algorithms are presented for fast and accurate transient analysis of power grid networks of high-speed designs. For this purpose, waveform relaxation based algorithms are advanced to handle the highly coupled systems of equations resulting from power-grid networks. In addition, advanced partitioning methods and mechanisms for fast convergence are developed. Also algorithms for fast sensitivity analysis of power-grid networks are described. Unlike the direct solvers, the new method is highly parallelizable and yields significant speed-ups. Numerical examples are presented to demonstrate the validity and efficiency of the proposed method.
Ram Achar, Associate Professor
Carleton University
Ottawa, ON K1S5B6,

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