Abstract Preview

Here is the abstract you requested from the IMAPS_2009 technical program page. This is the original abstract submitted by the author. Any changes to the technical content of the final manuscript published by IMAPS or the presentation that is given during the event is done by the author, not IMAPS.

Development of Wafer Level Embedded SiP (System in Package) for Mobile Applications
Keywords: wafer level process, embedded SiP, wafer level molding
Recently the requirement for portable products, such as mobile phones, digital cameras, PDAs and game consoles, has been increasing rapidly and consumers want to easy to carry them and have multi-functions as well as lower price. So its necessary to develop the semiconductor packages with thin and small size, high performance and low cost. And various types of SiP technologies have been developed to satisfy these requests. The embedded packages are one or more chips are embedded at the inside of the substrate and one of the technologies to realize the packages with thin and small size and high performance but there is much room for improvement, such as reliability issues, yields, etc. Therefore, wafer level embedded SiP (WL ESiP) which daughter chip is embedded on mother chip by mold compound without special substrate has been developed. To realize this SiP, redistribution, solder and Cu bumping, wafer level flip-chip bonding, wafer level molding, Si and mold thinning and ball mounting technologies has been applied. In this study, to confirm the structure of WL ESiP, the reliability tests of MSL2, PCT (121/ 100%RH/ 2atm), TC (-40/125) and HTS (150) had been performed for molded dies with various die size, dielectric materials and mold materials and they passed MSL2, 168hrs of PCT, 2000cycles of TC and 1000hrs of HTS. As a result of reliability tests, WL ESiP test vehicle was designed and fabricated to evaluate the package level and board level reliabilities. The size of mother and daughter chips is 4mm x4mm and 2.95mm x 2.31mm respectively and daughter chip has 70um thickness. Both of chips have daisy chains and electrically interconnected each other by solder bumps and these electrical chains are interconnected with redistribution layers on mold surface and solder balls to connect with the substrate. For the fabricated WL ESiP, package level reliability tests of MSL3, PCT (121/ 100%RH/ 2atm), TC (-40/125) and HTS (150) will be performed. And TC (-40/125) and drop (1500G/ 0.5ms) tests will be also performed at board level.
Gi-Jo Jung,
Nepes Corporation
Cheongwon-Gun, Chungbuk 363-883,

  • Amkor
  • ASE
  • Canon
  • Corning
  • EMD Performance Materials
  • Honeywell
  • Indium
  • Kester
  • Kyocera America
  • Master Bond
  • Micro Systems Technologies
  • MRSI
  • Palomar
  • Promex
  • Qualcomm
  • Quik-Pak
  • Raytheon
  • Specialty Coating Systems
  • Technic