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Interconnection Design and Impact Life Prediction Subjected to Board Level Drop Test
Keywords: Drop Test, Failure Prediction, Simulation
Accompanying the popularization of portable and handheld products, high reliability under the board level drop test is a great concern to semiconductor and electronic product manufacturers. In this study, a stress-buffer-enhanced package is proposed to meet the requirement of high drop impact performance. Both drop test experiment and numerical simulation were performed. The drop test experimental results showed a different failure mode observed in the stress-buffer-enhanced package. In the conventional wafer level package drop test analysis, solder joint cracks along IMC ( intermetallic compound) is the main cause of failure; however, in this study, for the fan-out type wafer level package with stress-buffer-enhanced design, failure in metal traces of packages instead of solder joint fractures is perceived. Because main failure of stress-buffer-enhanced package occurred at traces, the interconnection design becomes an important issue in the board level drop test. Straight trace layout and curved trace layout were experimented for the reliability assessment. Several drop test simulations were conducted to elucidate the mechanical behavior of PCB board and packages during the blink of impact. Based on the simulation results, a metal trace impact life prediction model is proposed for the stress-buffer-enhanced package to forecast the number of drops. Unlike the thermal cycle test, the dynamic response of drop impact is irregular and not in a cyclic characteristic; therefore, the concept of accumulated damage is considered in the life prediction model. The relation between accumulated plastic strain and drop number was correlated. There is good correlation between impact life predicted by simulations and measured by experiments. This approach provides both accurate simulation comparison and absolute impact life prediction. Based on the impact life prediction model, the methodology of design-on-simulation can significantly reduce the design cycles and meet the time-to-market requirement.
Kuo-Ning Chiang, Professor
National Tsing Hua University
HsinChu 300,
Taiwan


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