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Challenges of Supporting 3D IC and 3D Package Integration in the Design Space
Keywords: design, integration, package
The continued push for maximum functional and physical density in the smallest volume for the lowest cost has designers leveraging state-of-the-art 3D IC and 3D package integration schemes. In the last two years designers and manufacturers have seen a number of new integration technologies become viable -- TSV, Face-to-Face, and traditional wire bond die stacking in the IC space; PoP, PiP and TMV (through-mold-via) in the packaging space. Likewise, the boundaries between IC and package have started to blur, such that silicon itself has become a substrate material and an additional mechanism for 3D IC integration. Design tools that have traditionally fallen into tidy domains of IC, Package, and Board are not only being asked to support integration within their domains, but integration and co-design across the domains. This paper will outline the challenges and progress that package and pcb tools have had in moving from representing flat, layer based designs in one domain to being able to describe and support the complicated design hierarchy and 3D integration across multiple domains. Designers need to capture and maintain the partitioning and connectivity of the system, as well as being able to represent the manufacturing capabilities now available in the virtual design space. Likewise, the tools must not only be able to represent the 3D integration, but be able to export that design intent to analysis and complimentary design tools.
William Acito, Product Engineer, IC Packaging
Cadence Design Systems
Chelmsford, MA


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