Here is the abstract you requested from the IMAPS_2009 technical program page. This is the original abstract submitted by the author. Any changes to the technical content of the final manuscript published by IMAPS or the presentation that is given during the event is done by the author, not IMAPS.
|Thermal System Identification Analyses of Chip Interconnects to Facilitate DVFS Implementation|
|Keywords: DVFS, Thermo-mechanical reliability, Power fluctuations|
|With each advancing generation of process technology, the CPU power continues to rise, creating additional issues for thermal/mechanical packaging design. A common theme in next-generation CPU offerings will be the use of Dynamic Voltage and Frequency Scaling(DVFS) to manage the chip power during operation. With a DVFS policy, it becomes all the more important to study the potential impacts of imposed temporal variation in power on the thermo-mechanical reliability. In this study, we demonstrate a system identification approach for a practical CPU application and exemplify the trade-offs involved in creating a DVFS policy that is satisfactory to both thermal/mechanical reliability engineers and CPU design teams.|
Sun Microsystems Inc.
Santa Clara, CA