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Impact of Metal Fill on On-Chip Interconnect Performance
Keywords: metal fill, parasitic effects, on-chip interconnects
Advanced IC fabrication processes employ a Chemical Mechanical Polishing (CMP) to achieve uniform metal and dielectric thickness. The planarization achieved with CMP is good for local areas but it does not guarantee global uniformity. To achieve global uniformity, dummy metal fill structures are added in the low copper density areas. The floating or grounded metal fills result in capacitive and inductive parasitic effects. Previous work on metal fill has considered their parasitic effects, particularly capacitive. Recent research has also considered high frequency eddy-current loss in metal fills and its impact on the characteristics of spiral inductors and interconnects. It is important to study the impact of metal fills on on-chip transmission line structure as these topologies are gaining more importance for longer interconnections in high speed low power VLSI designs. The addition of metal fills leads to capacitive and inductive parasitic loading of interconnects. This in turn results in impedance mismatches, increased delay, dispersion and increased loss. This paper deals with analysis and design of on-chip interconnects considering metal fills. The first contribution of this work is to show the effects of metal fills on transmission line characteristics. We show the change in frequency dependent behavior of characteristic impedance and propagation constant when metal fills are inserted. We further study the impact of metal fill feature size on the transmission line characteristics. The second contribution of this work is design recommendations for on-chip transmission lines considering metal fills. For designed characteristic impedance, the losses in the structure are compared for different sizes of metal fills.
Vikas S. Shilimkar, Research Assistant
Oregon State University
Corvallis, OR

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