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Wafer Level Batch Fabrication of Silicon Microchannel Heat Sinks and Electrical Through-Silicon Vias for 3D Ics
Keywords: 3D Integration, Mircrochannel heatsink, Through-silicon Vias
Three-dimensional (3D) integration offers a multitude of advantages, including the ability to relieve the communication bottleneck present today in 2D IC systems. The stacking of chips greatly reduces interconnect length and latency as well as offers larger bandwidth at improved energy/bit. However, these benefits can be offset due to various thermal and power delivery challenges, especially for high performance logic stacking. In this paper, we describe a novel CMOS compatible process for the fabrication of microchannel heat sinks that can be integrated in a 3D stack of ICs. We propose a unique method of creating micro-fluidic channels that are etched in silicon and are enclosed using a thin silicon capping layer. A room temperature Si-Si direct bonding process is employed to cap the microchannels as opposed to conventional techniques that may not be conducive for further processing. Decoupling capacitors can be placed in the capping layer which can suppress power supply noise and in turn help tackle the power delivery problems in 3D ICs (models are reported in the paper). We also report a novel process to fabricate high aspect ratio through silicon vias (TSV) integrated with microchannel heat sink to enable electrical and fluidic interconnections in a single 3D chip. Thermal resistance and pressure drop in the microchannel heat sink are a function of the channel geometry; for example, increasing channel height can reduce thermal resistance and pressure drop. However, as the microchannel heat sink height increases, so does the aspect ratio of the TSVs (assuming fixed diameter). Other 3D integration technologies typically thin down the silicon wafer to a thickness of ~70m. However, the microchannel heat sink requires a silicon wafer thickness of ~250 m, and this fundamental difference imposes different constraints on electrical TSV fabrication and optimization. We report ~150-180 m deep microchannels with 100 m thick silicon capping layer and 50 m diameter electrical TSVs. Following the bonding of the chips, electrical and thermal measurements can be performed on this 3D test structure.
Jesal Zaveri, Student
Georgia Institute of Technology
Atlanta, GA

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