Heraeus ELD

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Lithography and Wafer Bonding Solutions for 3D Integration
Keywords: Thin wafer handling, temporary and permanent wafer bonding, lithography
The advantages as well as the technical feasibility of through silicon vias (TSV) have been acknowledged by the industry. Today the major focus is on the manufacturability and on the integration of all the different building blocks for TSVs and 3D Interconnects. In this paper the advances in the field of lithography, thin wafer processing and wafer bonding are presented with emphasis on the integration of all these process steps. Face-to-back integration schemes require the processing of thin wafers for both, wafer-to-wafer and chip-to-wafer stacking. Prior to thinning the device wafer is mounted on a carrier wafer with a temporary wafer bonding step. 300mm wafers with a thickness of 30m have been successfully processed through the complete TSV process line. Lithography on the backside of the thin device wafer requires alignment of the photo-mask to the alignment keys buried in the bond interface. After backside processing the thin wafer is debonded from the carrier wafer. The thin wafer is either mounted on dicing tape for singulation and subsequent chip-to-wafer stacking, or it is bonded immediately to another device wafer for wafer-to-wafer stacking. For applications with very high TSV density face-to-face integration schemes using Cu-Cu thermo-compression wafer bonding are a promising approach. Fusion bonding is very attractive due to the cost-of-ownership advantages compared to metal-metal bonding. Recent equipment and process improvements enable sub-micron alignment accuracy on 300mm wafers.
Thorsten Matthias, Director of Technology North America
EV Group
Tempe, AZ


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