Micross

Abstract Preview

Here is the abstract you requested from the IMAPS_2009 technical program page. This is the original abstract submitted by the author. Any changes to the technical content of the final manuscript published by IMAPS or the presentation that is given during the event is done by the author, not IMAPS.

Critical Issues of 3D High-Performance IC Integrations
Keywords: 3D high-performance interconnects, TSV, Microbumps
Moore's law has been the most powerful driver for the development of the microelectronic industry. This law emphasizes on lithography scaling and integration (in 2D) of all functions on a single chip, perhaps through system-on-chip (SoC). On the other hand, the integration of all these functions can be achieved through system-in-package (SiP) or, ultimately, 3D IC integration. There are many critical issues of 3D IC integration, especially for 3D high-performance interconnects, e.g., design guidelines & softwares are not commonly available; test methods and equipments are lacking; known-good-die (KGD) are required; fast chips mixed with slow chips; large chips mixed with small chips; microbumps usually are required; equipment accuracy for alignments; wafer thinning and thin wafer handling during processes; thermal management issues; 3D inspection issues; 3D expertises, infrastructure, and standards are lucking; TSVs usually are required for 3D high-performance interconnects; TSV cost is higher than wirebonding; TSV high-volume production tools are lacking/expensive; TSV design guidelines are not commonly available; TSV design softwares are lacking; TSV technology usually requires microbumps; test methodology and softwares of TSV are lacking; copper filling helps on thermal but increases TCE (thermal coefficient of expansion); copper filling takes a long time (low throughputs); the tough requirements of TSV wafer yields (>99.8%) due to the large number of vias; TSV wafer warpage due to TCE mismatch; thin TSV wafer handling during all the processes; TSV with high aspect ratios are difficult to manufacture at high yield; TSV inspection methodology; TSV expertises, infrastructure, and standards are lucking. In this paper, most of the critical issues of 3D high-performance interconnects will be discussed and some potential solutions or research problems will be proposed.
John H. Lau, Visiting Professor
HKUST
Kowloon, Hong Kong 123456,
China


CORPORATE PREMIER MEMBERS
  • Amkor
  • ASE
  • Canon
  • EMD Performance Materials
  • Honeywell
  • Indium
  • Kester
  • Kyocera America
  • Master Bond
  • Micro Systems Technologies
  • MRSI
  • NGK NTK
  • Palomar
  • Plexus
  • Promex
  • Qualcomm
  • Quik-Pak
  • Raytheon
  • Specialty Coating Systems