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Advanced Wafer-Level Integration Technology with Ultra Fine Pitch Redistributed Layers between Heterogeneous Devices
Keywords: Wafer-Level Integration, pseudo-SOC, Redistributed Layers
High density integration of heterogeneous devices such as LSI, passive components or MEMS has been being required due to radical miniaturization of electronic devices. The authors have proposed Pseudo-SOC Technology realizing integration of heterogeneous devices with resin and have established basic key technologies [1]. In this paper, the authors show the overview of the technology as well as the results of the ultimate refinement of redistributed layer on the pseudo-SOC as the state of the art. It is indispensable to integrate heterogeneous devices with narrow gap and to interconnect them with fine pitch redistributed layer (global layer) to realize high-density integration in the pseudo-SOC. Resin must be filled into the narrow gap without voids, since the existence of the surface step may lead to the breaking of the redistributed layer. In this study, vacuum printing condition was optimized for forming resin in the narrow gap without voids. Furthermore, the step was reduced to less than 1um by optimizing the condition of mounting devices and forming planar layer. Adhesion of the redistributed layer was also optimized by tuning plasma treatment on underlying layer to suppress the peeling of the redistributed layer. As a result, a fine pitch redistributed layer with as narrow as 1um/1um in line/space was realized on the pseudo-SOC. Finally, a pseudo-SOC where CMOS-LSI and MEMS were integrated and connected with fine pitch redistributed layers was fabricated and the operation was also confirmed successfully. The effective volume was less than 10 cubic millimeters. From these results, it was confirmed that high density integration of heterogeneous devices is realized by the advanced pseudo-SOC technology. [1] Y. Onozuka et al., Wafer-level integration technology with heterogeneous chip redistribution and inter-chip layer process, Proceeding of IMAPS 40th International Symposium on Microelectronics, pp.777-784, Nov.2007.
Yutaka Onozuka, Research Scientist
Toshiba Corporation
Kawasaki, Kanagawa 212-8582,

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