Here is the abstract you requested from the IMAPS_2009 technical program page. This is the original abstract submitted by the author. Any changes to the technical content of the final manuscript published by IMAPS or the presentation that is given during the event is done by the author, not IMAPS.
|Mechanically Punched Micro Via Fabrication Process in LCP Substrate for RF-MEMS and Related Electronic Packaging Applications|
|Keywords: Liquid Crystal Polymer (LCP) Substrate, Mechanical Punching of Micro Vias, RF-MEMS Packaging|
|The objective of the research is to develop fundamental understanding of the mechanical punching process for fabrication of micro vias on liquid crystal polymer (LCP) substrate. LCP is attracting significant interest in electronic packaging for RF and microwave applications, including RF-MEMS packaging. Various surface and subsurface features such as micro vias and cavities, at low cost are critical for the fabrication of RF-MEMS packaging. In this research we have successfully demonstrated a cost effective micro mechanical punching process for the fabrication of through vias of different sizes and pitch on LCP substrate (Rogers Corporation; ULTRALAM 3850TM) of 50 µm thickness with ½ oz. (20 µm) copper cladded on both the sides. Fabricated test vehicle consisted of an array of micro vias (n x n; n = 2, 4, 6, 10) along with a pitch starting from 1.5 time of via diameter with 25 µm increments. Vias of as small as 50 µm in diameter have been successfully fabricated with the pitch of as small as 75 µm desired for RF-MEMS packaging. We observed a z-axis expansion of the LCP film, which has strong dependency on areal density of micro vias, and the pitch used for via fabrication, where the smallest pitch has the highest Z-axis expansion (1.5-1.8 times). Another interesting observation is that the lower punch speed (2-4 punch/sec) tends to leave residual LCP burr inside the vias, which needs to be cleaned before further metallization of vias. Microhardness and X-ray diffraction (XRD) techniques were applied to determine possible strain hardening and residual stress respectively, built in the top copper layer in the vicinity of micro vias. Measurement showed no trace of strain hardening, and residual stress buildup in the vicinity of via array. This promising micro via fabrication technique could be integrated into high yield fabrication line for a time efficient low cost manufacturing processes.|
|Mohammad K. Chowdhury, Graduate Student
University of Arkansas