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Electromigration and Annealing Kinetics of Cu Pillar Bump
Keywords: 3D IC package, electromigration, Cu pillar bump
Flip chip packaging technology has been widely used in the electronics industry in recent years as high performance and miniaturized electronics have become more common. This technology assists in the achievement of high performance and miniaturization because the chip and the substrate are directly connected to solder bumps. The solder bumps become spherical to minimize the surface energy. Bump bridging is caused by the shape of solder in miniaturized electronics. It is limited to applications with a fine pitch. Therefore, a new shape for the bump structure is necessary to address this limitation. Cu pillar bumps are known to be one of the most promising candidates for the fine pitch interconnection materials because they do not cause bump bridging between adjacent bumps. However, Cu pillar makes large amount of intermetallic compound with solder at solder joint. Not only excessive intermetallic compound growth but also Kirkendall void formation between Cu pillar and solder can degrade mechanical reliability. Therefore, it is necessary to understand the intermetallic compound and Kirkendall void growth kinetics. In this work, we performed kinetic studies on the Cu pillar/Sn bump structure in order to quantify the amount of IMC and Kirkendall void during current stressing.
Youngbae Park, Professor
Andong National University
Andong, Gyungbuk 760-749,
South Korea


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