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Laser Based Assembly of Ultra Fine Pitch Bumped ICs for Die-on-Die Applications
Keywords: Flip Chip, 3D, die stacking
For most traditional solder bumping applications on semiconductor wafers, the bumps range in height from around 50 um up to 300 um. The solder bumps at the lower end of this range are often referred to as flip chip bumps (FC) and those at the higher end of this range are called wafer level chip scale packaging bumps (WLCSP). For some applications, like chip-on-chip, 3D die stacking, and inductively coupled devices, the use of these ‘large” solder bumps is not ideal because it increases the overall size of the system, limits interconnect density, and also contributes to parasitics which affect the electrical performance. The use of micro-bumps to create this thin interconnect is one method that allows for some versatility. By using wafer-level-packaging techniques (WLP) to create these micro bumps, one can take advantage of the infrastructure that already exists within packaging subcontractors. These wafer level processes include: redistribution, UBM deposition, solder bumping, thin film deposition, and wafer thinning. In this paper, we describe the use of e-Ni/Au and a liftoff process to create very thin bumps at the wafer level. Electroless nickel/gold is first deposited onto the bond pads of the wafer using a series of sequential wet chemical techniques. A liftoff resist is then applied to the wafer and photo lithographically patterned. This is then followed by the sputter deposition of a thin layer of metal solder and stripping of the liftoff resist. These bumped wafers are then thinned, diced, and sorted into waffle packs. Assembly is accomplished by aligning the bumped die to the corresponding unbumped second die and laser heating to reflow the solder and form the interconnect. The bonding and laser heating variables will also be discussed in this paper.
Andrew Strandjord, Senior Manager Advanced Packaging
PacTech
Santa Clara, CA


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