Here is the abstract you requested from the IMAPS_2009 technical program page. This is the original abstract submitted by the author. Any changes to the technical content of the final manuscript published by IMAPS or the presentation that is given during the event is done by the author, not IMAPS.
|Design and Process of 3D MEMS Packaging|
|Keywords: 3D MEMS Packaging, TSV, SiP|
|Advanced 3D MEMS packaging usually involves 3 wafers, namely the MEMS device wafer, the ASIC wafer, and the cavity cap wafer. In this study, the design and process of 10 different designs of 3D MEMS packaging will be presented and discussed. These 3D MEMS packages integrate the MEMS devices from the MEMS wafer (with either wirebonding pads, or solder-bumped TSV substrate, or solder-bumped flip chip without TSV), the ASIC chips from the ASIC wafer (with either TSV or without), and the cavity package cap from the cap wafer (with either TSV or without). The assembly process consists of release (etching), singulation, wire bonding, flip chip, TSV, cavity etching, chip-to-wafer (C2W) and wafer-to-wafer (W2W) bondings. It can be shown that these packages are supposed to yield very low-cost, high performance and less packaging foot-print.|
|John H. Lau, Visiting Professor
Kowloon, Hong Kong 123456,