Here is the abstract you requested from the IMAPS_2009 technical program page. This is the original abstract submitted by the author. Any changes to the technical content of the final manuscript published by IMAPS or the presentation that is given during the event is done by the author, not IMAPS.
|An Interconnection Verification Method and a New Substrate Option for Cu Pillar Flip-chip Module Applications|
|Keywords: Cu pillar flip chip, Assembly DOE, Reliability, Low Cost|
|Cu pillar flip-chip technology has been in development and production for several years. It has clear advantages over solder flip chip. These advantages include fine pitch capability, flexible bump shape, and short thermal/electrical path. Challenges in the assembly process are also well known. This paper introduces an easy and effective test method to verify the interconnection quality between Cu pillar flip chip and substrates for a volume production environment. Qualification lots using this process were built and passed a full range of reliability tests. The reliability of the Cu pillar flip-chip modules that were assembled on Au surface finish substrates was also evaluated. The study shows the feasibility of a low cost option to assemble flip chip and wire bond die on the same substrate.|
|Shannon Pan, Engineer
RF Micro Devices