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A Low Power CMOS 60GHz Transceiver with LTCC On-Package Patch Antenna
Keywords: 60GHz CMOS Transceiver, LTCC Packaging, On-package antenna
This paper presents a low power 60GHz transceiver which includes RF, LO, PLL and BB integrated into a single chip and has been packaged into an LTCC package with integrated antennas. The transceiver has been fabricated in a standard 90nm CMOS process and includes ESD protection on all pads include those carrying mm-wave signals. With a 1.2V supply, the chip consumes 170mW while transmitting (+10dBm) and 138mW while receiving. Using on-wafer probing, data transmission up to 5Gbps on each of I and Q channels has been measured, as has data reception over a 1m wireless link at 4Gbps QPSK with less than 1E-11 BER. We plan to perform similar measurements in the package. The die has been integrated into the LTCC package using flip-chip solder bumps. The LTCC package houses a 16-element patch antenna array to achieve directional gain with good efficiency. Microstrip-based low-loss feedlines have been used to connect the PA/LNA output/input to the antenna array.
Maryam Tabesh, Graduate Student Researcher
UC Berkeley & Technical Research Centre of Finland (VTT)
Berkeley, CA


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