Here is the abstract you requested from the Wirebond_2009 technical program page. This is the original abstract submitted by the author. Any changes to the technical content of the final manuscript published by IMAPS or the presentation that is given during the event is done by the author, not IMAPS.
|HAZ-Free Ultra-Low Loop Method for Multi-Chip Stacked Die Applications|
|Keywords: Stacked die, wirebonding, ultra low loop|
|The ever increasing demand for higher device memory capacity and functionality, has resulted in Stacked-die technology that allows not only to carry on the prediction of Moore’s law -doubling of IC density approximately every two years, but has in the same manner continued to push the limit in the number of die tier to double digits. Wirebonding multi-layered packages have always required an ultra-low loop process in order to accommodate die-stacking with the thinnest package possible. From the processing side, as the number of die-stack continues to grow, so is the number of strip transport passes in which the package has to undergo repetitive mechanical strain from die attach and wirebond stations. It is in this scenario, that the perennial stress on the ball neck as a result of the Heat-affected Zone becomes an area of concern as it is amplified by the multiple pass processing. This paper presents a novel method of Au ball bonding ultra low loop applications that improves the reliability of the weld-wire junction by removing the effects of grain growth (HAZ) which is the weak zone of the bondwire. This means that the number of succeeding passes that a multi-chip process requires is no longer limited by the mechanical strain that the first wirebond pass is able to absorb. In this paper, the new first-bond “double-wedge” process is described as an alternate to the traditional first-bond “ball-neck” profile.|
|Jovy Michael G. Sena, Senior Service Engineer
Besi North America, Inc.