Abstract Preview

Here is the abstract you requested from the Wirebond_2009 technical program page. This is the original abstract submitted by the author. Any changes to the technical content of the final manuscript published by IMAPS or the presentation that is given during the event is done by the author, not IMAPS.

Bond Wire Yield Rate Optimization on SiP in a 3D Design Environment
Keywords: Bond Wire , 3D Package Design , SiP
IC packaging layout has traditionally been done using conventional 2-D layout software. While 2D design tools are sufficient for single die top-down 2D type packages such as lead-frames and simple BGAs, traditional design rule checks (DRC) included in 2D layout tools are not able to confirm or simulate efficient 3D wire bonding assembly of advanced System-in-Package (SiP) designs such as Stacked Die, stacked and folded packages, and densely wired I.C.s with multiple power rings and multiple bond shells. The package designer currently completes the design in 2D, not knowing if the 3D package he designed is truly manufacturable or not. The manufacturing engineer is thus forced to perform a long series of trial-and-error prototype wire bonding runs, which take substantial time. The package may be mass-produced with resultant low yields, contributing to higher costs and further increasing time-to-market, and can ultimately require a complete redesign after much wasted time and resources. Dramatically improved reliability and yield, and decrease time-to-market for stacked die packages, densely wire bonded I.C.s and other 3D package types are possible with a 3D design and collaboration process which integrates the design, optimization, verification, manufacturing and inspection processes into a globally accessible seamless system. A 3D design and collaboration system provides data access to all related departments to optimize the design for maximum performance, highest yield and fastest time-to-market. The package designers can input 3D wire bond assembly parameters during the design process. The design is modeled in 3D, and the assembly parameters are simulated, verified, and optimized for maximum yield during the design process. Providing the design engineer access to 3D wire bond profiles and a method to verify the design for possible wire bond interference violations dramatically shortens the design cycle time and leads to better and more manufacturable designs. Additionally, the 3D wire bond data can also be sent to analysis tools for full simulation of wire bonds, which is imperative for high speed designs. When the resultant optimized design arrives in production, the trial-and-error prone set-up process can be dramatically reduced, and the resultant Yield Rate can be vastly improved.
John R. Sovinsky , CTO
CAD Design Software
San Jose, CA

  • Amkor
  • ASE
  • Canon
  • EMD Performance Materials
  • Honeywell
  • Indium
  • Kester
  • Kyocera America
  • Master Bond
  • Micro Systems Technologies
  • MRSI
  • Palomar
  • Plexus
  • Promex
  • Qualcomm
  • Quik-Pak
  • Raytheon
  • Specialty Coating Systems