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Simulation of Process-Stress Induced Warpage of Silicon Wafers Using ANSYS® Finite Element Analysis
Keywords: Wafer Warpage, Intrinsic Stress , Saddle Wafers
Wafers warp. It is important to minimize warpage in order to achieve optimal die yield and potentially prevent future device failure. Although the word “warpage” is widely used in the literature to represent wafer bow (convex or concave shape), in the real world wafers are often seen into warp into saddle shapes. This complicates the characterization of both the sources of and solutions to warpage, because (as will be discussed) Stoney's formula (relating intrinsic stress and curvature) does not apply for structures warped with compound curvature, and standard wafer warpage measurements are not designed to measure compound curvature. During thin film deposition, wafer warpage occurs due to the intrinsic stresses and the coefficient of thermal expansion (CTE) mismatch of the different thin films and the substrate. Unfortunately, whereas the introduction of the thermal stresses due to CTE mismatch into a finite element model is easily understood, the introduction of intrinsic stress is not. Further, although a saddle shape is clearly a physically realizable (indeed, often preferred) equilibrium configuration for a circular disk (consistent with an appropriate state of stress), obtaining a saddle shape in a finite element solution turns out to be extremely difficult, as convex or concave shapes may also be stable and numerically preferred. In this paper, a finite element technique (using ANSYS software) to model wafer warpage is presented. Simulations have been done for silicon wafers with aluminum or standard UBM films on top. Saddle-shaped warpage has been successfully modeled, and the aggravating effects of thinning (back side grinding) have been reproduced.
Aditi Mallik, Principal Research Engineer
ON Semiconductor
Phoenix, AZ

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