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The Use of Metallographic and SEM Analysis for Characterization of Sidewall Surfaces in MEMS Devices with DRIE Processing
Keywords: MEMS Packaging, Bosch DRIE Etch, SEM Analysis
The use of Bosch process Deep Reactive Ion Etch (DRIE) processing for manufacturing MEMS and MOEMS devices requiring high aspect ratio (depth/width) trenches has become commonplace. However, process conditions (etch rate, process parameters etc.) have a significant effect on the surface quality of the trench sidewalls. For many device types [1], [2] (grates, waveguides) surface condition of the sidewall can have a large impact on the functionality of the device and therefore must be controlled to achieve performance requirements. Optical microscopy techniques are not capable of the depth of focus and resolution necessary to adequately control processing within deep trenches where surface roughness of < 10nm may be required. Scanning Electron Microscopy (SEM) is capable of this resolution, but even SEM is incapable of determining surface roughness within the deep trenches. Metallographic techniques, mounting and polishing a sample to reveal a section view through the trench, along with SEM, to image and measure the surface roughness is a requirement. An experiment was designed, using etching parameters to vary the DRIE recipe, and then cross sectioning and SEM imaging of the devices were performed. The purpose of the experiment was to quantify the effect of the DRIE recipe on the sidewall surface roughness within the trench, and to demonstrate the use of metallographic techniques with SEM to accomplish this goal. TEST ARTICLE Micromachined Si test articles were designed and fabricated. Each test article consisted of a Si die, 1cm x 1cm and nominally 375µm thick, with a DRIE etched trench in the center. The trench was 8mm long and 50µm wide. An illustration (not to scale) of the test article is presented in Figure 1. As the parameters of the DRIE fabrication process were adjusted, the test article was utilized as a vehicle for evaluating side wall roughness of the etched trench. For this investigation, an STS ASE (Advanced Silicon Etcher) was utilized for the DRIE process. A photograph of the STS ASE in the Auburn University Microfabrication Facility is presented in Figure 2. The Si test articles were fabricated out of double-side polished, 100mm diameter, 375µm thick, (100) crystal orientation, boron doped (1-10Ω-cm resistivity) Si wafers. 49 die, in a 7x7 array, were fabricated on a single wafer. Fabrication began with a thorough cleaning of the wafer. Then the wafer was prepared for photolithography by vapor coating with HMDS (hexamethyldisilazane) to promote photoresist adhesion. This was followed by spin coating with AZ4620 photoresist to achieve a nominally 6.5µm thick layer. After a soft bake cycle, contact photolithography was performed, followed by developing and a hard bake cycle. After inspection, the wafer was diced to singulate the individual die. A second Si wafer, called the backing wafer, was similarly coated with AZ4620 photoresist. Five die were then mounted on the photoresist layer on the backing wafer. After a bake cycle, the backing wafer was placed into the STS ASE for DRIE etching of the trench in each die. After DRIE was completed, the individual die were removed from the backing wafer with a solvent and then O2 plasma cleaned to remove the sidewall polymerization and any remaining photoresist. DRIE Deep reactive ion etching is based on the 1996 patented Bosch process, which uses a sequential alternating process of etching and passivation. Using this process, aspect ratios of greater than 20 have been achieved. This etching process is therefore widely used to etch deep structures (100mm and deeper). The first step is an SF6/Ar plasma RIE etch. After a short time, the etching process is halted and replaced with the passivation step. During this process, all exposed surfaces, horizontal and vertical, are coated with a polymer layer, approximately 50nm thick. The polymer layer is similar to Teflonä, and is typically a chemical combination of C4F8 and SF6, which chemically forms polymerized CF2 in the plasma reactor. Then the etching step is performed again, which rapidly removes the passivation layer on horizontal surfaces but not on vertical surfaces. This results in continued vertical etching of the substrate without significant horizontal etching. Alternation of the etching and passivation processes continues until the desired etch depth is reached. With this etching process, smooth sidewalls are not achieved. In fact, the sidewalls contain horizontal microtrenches that delineate individual etch/passivation cycles. This phenomenon is called scalloping. Since they are numerous DRIE parameters that can be adjusted for various reasons, such as plasma chemistry and pressure, RF plasma power, platen bias RF power, etch time, etc…, the scalloping effect varies greatly between DRIE processes. METALLOGRAPHY Two samples of each treatment condition were metallurgically mounted, cross-sectioned perpendicular to the length of the trench and polished in preparation for SEM analysis of the sidewall roughness and draft. Two other samples of each treatment were fractured along the length of the trench for imaging of the trench sidewalls and for laser profilometer measurements. SEM ANALYSIS Measurement of device features by the SEM requires good calibration and also a good understanding of the geometry. Because of the large depth that is in focus, images appear almost in a 3-D view, but SEM based measurement systems are simple pixel counters. Understanding which features represent true dimensions and which have been foreshortened by the perspective offered by the depth of focus is required for accurate measurements. Roughness and taper of the etched sidewalls was evaluated using the measurement system on the SEM. In addition, a laser profilometer was used to measure surface roughness. CONCLUSION Process control for the Bosch DRIE process requires characterization of the etched sidewalls. For some products, this requires nanometer scale measurement capability. Development of measurement tools capable of these measurements must come before good process control can be achieved. Bibliography [1] H.C Liu, Y.H. Lin, W. Hsu, “Sidewall roughness control in advanced silicon etch process”, Microsystem Technologies 10(2003), 29-34 [2] P. Mukherjee, M.G. Kang, T. Zurbuchen, L.J. Guo, F. Herrero, „Fabrication of high aspect ratio Si nano gratings with smooth sidewalls“, J. Vac. Sci. Technol B, 25(6), Nov/Dec
Lee Levine, Consultant
Process Solutions Consulting
New Tripoli, PA
USA


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