Micross

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Processing Aspects to Achieve High-End Hybrid Backside Illuminated Imagers
Keywords: back-side illuminated imager, processing, high quantum efficiency
We present a processing scheme of a backside illuminated 1024x1024 pixel sensor array, flip chipped on top of a ROIC with 22.5 um pitch micro bumps. Backside illumination results, as compared to front side illumination, in a large gain in quantum efficiency because no incoming light is lost in the metal and dielectric layers. At the other side however, backside illuminated imagers requires more complex post processing because the detector array has to be thinned down to 30um or less. Surface treatment reduces surface combination and lead to an improvement of the quantum efficiency of the device. These critical cleaning steps are done after thinning and before anti reflective coating deposition. Any damage induced at the backside of the imager is detrimental for the quantum efficiency since defects act as recombination centers for the light generated electron-hole pairs. Cross-talk reduction is obtained by the introduction of high aspect ratio pixel separating trenches; also here cleaning steps are crucial. Next to the discussion on the critical steps (such as wafer thinning on carrier, wafer flip, cleaning), two possible routes for micro bumping are shown. Both In lift-off as CuSnCu electroplating micro bump formation are shown (1M bumps, 20um pitch). For space applications, radiation tolerance is an important parameter. Adaptations around field oxide regions are tackled. Also a novel backside alignment strategy to avoid using pyrex substrate as temporary carrier for thinning is included. Pyrex is namely not compatible in a high-end Si process environment due to its fragile nature. In the end all process optimizations on the hybrid backside illuminated imager device lead towards a quantum efficiency of 80-90% (over the visible spectrum).
Joeri De Vos, Senior Process Integration Engineer
IMEC
Heverlee, Vlaams-Brabant 3001,
Belgium


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