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|Wafer-Level Hermetic Packaging for Bio-Medical Applications|
|Keywords: Wafer-level, Packaging, Bio-medical|
|With the advent of modern life sciences and healthcare in the recent years, it has become conceivable to integrate electronics as implant into the human body. In-vivo applications present strong requirements in terms of bio-compatibility: a device for such applications must be packaged in way to protect firstly the body from harmful substances, e.g. metals as Cu, and then to protect the device itself from possible body interaction that could damage its functionalities. We report on a wafer level encapsulation process aiming at encapsulating commodity Integrated Circuits (IC). The encapsulation consists of a stack of layers, to prevent diffusion of metal contaminant, prior to final encapsulation in a bio-compatible package. The reported process relies on classical CMOS and 3D wafer-level packaging manufacturing equipment. The test devices for encapsulation consist in test silicon chips with Cu metal structures designed to be characterized in a standard ‘daisy chain' configuration. A double diffusion barrier is created on the top side of the chip to avoid Cu diffusion. The first barrier consists on a thick layer of Silicon nitride which offers superior performance with respect to Cu diffusion in the immediate vicinity of the interconnect layers. After this step the wafer is processed with Dicing-Before-Grinding (DBG) technique. A thick silicon oxide is deposited on the sidewalls of the pre-grooved wafers to protect the edge of the IC dies, prior to thinning the wafer down to 80µm. The backside of the IC dies is then rounded and followed by a 3µm thick oxide deposited at low temperature to finish the encapsulation. Finally, the test chips are debonded and cleaned. The effectiveness of the encapsulation process will be assessed by means of in-vitro cell culture tests. Data will be presented.|
|Antonio La Manna,
Leuven, Flanders B-3001,