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PCB Effects on On-Chip Capacitor Requirements and an Efficient Resonance-Prevention ASIC Methodology
Keywords: On-chip decoupling, Chip-package-PCB resonance, Resonant frequency
On-chip capacitors, which provide local reservoirs of charge, have been recognized for some time as necessary components of robust microelectronic power delivery networks (PDN). A method for determining adequate quantities and locations of on-chip capacitors to maintain supply voltages at all locations on a chip within pre-specified limits given the switching activity of on-chip circuits was presented in [1]. The method accounts for charge moved by on-chip circuits, but assumes no additional charge is delivered to the chip during the period of switching activity. In this paper, we extend the method to include current flow from the package and PCB. The effects of on-chip capacitance and other system parasitics on the time it takes for additional supply current to flow into a chip are discussed. The relationship between switching current, capacitance, system parasitic inductances, and on-chip noise is presented. These concepts are then applied to the subject of PDN resonance. Increased PDN noise owing to resonance is particularly likely when a system has wide sub-GHz busses such as those encountered in typical DDR3 interfaces. Such busses can operate at frequencies that are in the range of natural resonances of typical PDNs. Particular bus data patterns may be capable of exciting those resonances, thereby pumping noise onto the supply rails of a chip. Such resonant power noise is detrimental to system operation because it introduces additional, unaccounted for jitter on critically timed logic paths and system interfaces. A 1-dimensional model for simulating PDN resonance is presented. The model includes chip, package, and PCB components, along with explicit networks for each chip power supply and their interactions. The topology of the the model and the contributions of each model component are described. A design methodology for avoiding PDN resonance, presently in use on all IBM ASIC modules, is presented. [1] Nanju Na, Timothy Budell, Charles Chiu, Eric Tremble, and Ivan Wemple,
Timothy Budell, Senior Engineer - Image/Package Development
International Business Machines
Essex Junction, VT
USA


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