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Molded Underfill (MUF) Technology Development for SiP Module With Fine Flip Chip
Keywords: Molded Underfill (MUF), System In Package module (SiP), Fine pitch Flip chip
In this study, we developed the Molded Underfill (MUF) technology for system in package (SiP) module with fine pitch flip chip in RF application, in which two flip chips, LC filter, and additional passive components are integrated side-by-side. This study covered not only MUF reliability performance but also MUF design study focused on the void free methodology to minimize void between flip chip bumps, process parameter design of experiment (DOE), and reliability performance of the SiP module. The investigation comprises several aspects: A design study, that present a printed circuit board (PCB), and epoxy molding Compound (EMC) selection approach, gate & air vent design of cavity vacuum molding, and process evaluation methodology for SiP module. The test vehicle used for this study of MUF by vacuum transfer molding was shown SiP module (8.2x7.7x1.13mm) which was sawn from 52.70x68.70x0.75mm mold area. 52.70x 68.70x0.75mm one segment mold inside had 35ea SiP modules (7X5 unit array). In addition, one SiP module included one Flip chip RF/BB IC(6.51x5.81x0.41mm) which had 339ea bumps and 95um Bump height, one Flip chip RF switch (0.705x0.705x 0.33) which had 4 bumps and 85um bump height, 1.6x0.8x0.6mm size of LC filter, and total 25ea passives. In the end, moisture sensitivity test, thermal cycle test and pressure cooker test had also been carried out for reliability evaluation. The test results shows that the optimized SiP module with fine flip pitch has a good reliability performance.
DoJae Yoo, Senior Research Engineer
Samsung Electro-Mechanics Co., Ltd.
Suwon, Kyunggi-Do 443-743,
South Korea

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