Here is the abstract you requested from the IMAPS_2010 technical program page. This is the original abstract submitted by the author. Any changes to the technical content of the final manuscript published by IMAPS or the presentation that is given during the event is done by the author, not IMAPS.
|3D IC Technology: The Perfect Storm|
|Keywords: 3D IC, IC Scaling, 3D Economics|
|IC technology up to now has been dominated by shrinking gate dimensions and decreasing operating voltage. Unfortunately, interconnect shrinkage has had a negative effect on device performance since smaller cross section wire dimensions have increased resistance and tighter pitches have raised capacitance resulting in an increase in RC delay. At the same time clock speed has leveled off due to the thermal restrictions placed on systems by air cooling. Memory latency (the number of cycles needed to access main memory) has also suffered, especially with today's multicore processors. All of these technical issues have combined with the cost of today's sub 45 nm node foundry to create a "Perfect Storm" scenario which is ushering in the era of 3-D IC. All of these issued will be described and discussed. The implications of 3D IC on device design, system design and packaging as we know it will be discussed.|
|Philip Garrou, Consultants
Microelectronic Consultants of NC