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Low Temperature Bonding of High Density Large Area Array Interconnects for 3D Integration
Keywords: 3D Integration, High Density Metal to Metal Bonding, Cu Micropillar Interconnect
High density interconnect enables further miniaturization, reduced power consumption and enhanced functionality of microsystems. In addition, heterogeneous technologies such as sensors, MEMS, imaging arrays and others can be implemented in their optimal process flows and then integrated through 3D integration. A number of research groups have presented work in the area of metal-metal interconnect [1, 2, 3]. Previous work at RTI has demonstrated bonding processes and estimated yield for 50µm and 25µm pitch area array interconnects with both Cu/Sn-Cu and Cu-Cu bump bonding [4-7]. In the current work a high yield bonding process is described based on a 512x640 area array test vehicle with 10µm interconnect pitch, representing a density of 10^6 interconnects per cm^2. Processes for bonding Cu/Sn-Cu and Cu-Cu metal-metal interconnects are described. The CMOS-compatible fabrication process is presented, including patterning and electroplating of 4µm diameter pads with 4µm thick Cu and 2µm thick Sn. The interconnect bonding process resulted in the formation of low resistance (<100 mΩ), high yielding (99.99% individual bond yield) mechanically reliable interconnects. We will present SEM cross sections of Cu/Sn-Cu and Cu-Cu bonded samples and EDS analysis of Cu/Sn intermetallic compounds both before and after stress testing, and discuss effects of thermal cycling on electrical yield and resistance for Cu/Sn-Cu bonds with underfill. We will compare electrical and shear test performance of Cu/Sn-Cu and Cu-Cu bonds and present results for forming Cu/Sn-Cu bonds at 210°C and below which resulted in similar performance to bonding at temperatures above the melting point of Sn. These lower temperature bonding processes are of interest for compatibility with thermal budgets of some CMOS and MEMS devices. References [1] K. Tanida, M. Umemoto, Y Tomita, M. Tago, Y Nemoto, T. Ando, and K. Takahashi, “Ultra-high-density 3D Chip Stacking Technology,” Proc. of 2003 ECTC, New Orleans, LA, May 2003, pp. 1084-1089. [2] A. Klumpp, R. Merkel, R. Wieland, and P. Ramm, “Chip-to-Wafer Stacking Technology for 3D System Integration,” Proc. of 2003 ECTC, New Orleans, LA, May 2003, pp. 1080-1083. [3] S. Pozder, A. Jain, R. Chatterjee, Z. Huang, R. Jones, E. Acosta, B. Marlin, G. Hillman, M. Sobczak, G. Kreindl, S. Kanagavel, H. Kostner, S. Pargfrieder, “3D Die to wafer Cu/Sn microconnects formed simultaneously with an adhesive dielectric bond using thermal compression bonding”, proc. of 11th IITC 2008, pp 46-48. [4] A. Huffman, M. Lueck, C. Bower, D. Temple, “Effects of Assembly Process Parameters on the Structure and Thermal Stability of Sn-capped Cu Bump Bonds,” Proc. 2007 Electronic Components and Technology Conference, Reno, May - June 2007, pp 375-381. [5] A. Huffman, J. Lannon, M. Lueck, C. Gregory, & D. Temple, “Fabrication and characterization of metal-to-metal interconnect structures for 3-D integration”, Materials and Technologies for 3-D Integration, MRS Symposium Proceedings, Vol. 1112, Boston, MA, December 2008, pp 107-120. [6] J. Lannon Jr., C. Gregory, M. Lueck, A. Huffman, and D. Temple, “High Density Cu-Cu Interconnect Bonding for 3-D Integration”, Proc. of 2009 Electronic Components and Technology Conference, San Diego, May 2009, pp 207- 213. [7] A. Huffman, C. Gregory, M. Lueck, J. Reed, D. Temple, and R. Stapleton “Evaluation of Cu/Sn-Cu Bump Bonding Processes for 3D Integration Using a Fluxing Adhesive”, presented at 2010 IMAPS International Conference and Exhibition on Device Packaging, Scottsdale/Fountain Hills, AZ, March 2010.
Jason Reed, Engineer
RTI International
RTP, NC
USA


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