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Filling and Planarizing Deep Trenches With Polymer for Through-Silicon Via Technology
Keywords: Trench Fill, Via Fill, Planarization
Three-dimensional (3D) integration allows for smaller, faster, and more functional microelectronic devices. Through-silicon via (TSV) technology enables through-chip communication and has been a key driver for 3D device integration. TSVs typically have an electrical isolation using a dielectric layer between silicon and the interconnect metal (e.g., copper). Recently, polymers have been proposed for use as the dielectric isolation layer. In addition, polymers have been shown to increase device reliability by reducing “copper pumping,” where copper pops out from the TSV holes during thermal cycling due to the combination of CTE mismatch, aspect ratio of the holes, and the hole diameter. Traditionally, spin or spray coating techniques have been used to fill TSVs with polymer material. But such processes alone have depth limitations. Filling and planarizing very deep trenches (~400 µm) and high-aspect-ratio structures using just spin and spray coating techniques are difficult and usually result in voids, nonplanar surfaces, and lack of polymer flow to the requisite depths. We present a process and a tool to completely fill and planarize deep trenches with a polymeric material. In this process, polymeric material is spin coated on the trench wafer and baked using standard processing conditions. Then a pressure film, treated to make it non-stick, is placed on top of the wafer surface, and this assembly is transferred to the process chamber inside the planarization tool. The wafer/pressure film assembly is held in the process chamber under vacuum, and an infrared light source heats the polymer layer. After a short soak (~2 minutes), pressure is applied to the wafer and the pressure film. The pressure film compresses and pushes the excess polymeric material that is on top of the wafer topography inside the vias and trenches to completely fill the features without any voids. The IR light source heats only the polymeric material and not the silicon wafer, which considerably shortens the planarization process time. After planarization, the wafer/pressure film assembly is moved to the delamination chamber in the tool, where the film is pulled away from the wafer. The treated pressure film allows it to be easily delaminated from the polymer surface without sticking. Finally, the planarized wafer is removed from the tool for further processing. Using this process, we successfully filled and planarized trenches and vias 180 µm deep with 50-µm wide patterns as well as 400-µm deep trenches with ~400-µm wide patterns. Initial results show complete filling and planarization of the material in the trenches without any voids.
Ramachandran K. Trichur, Principal Engineer
Brewer Science, Inc.
Rolla, MO
USA


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