Here is the abstract you requested from the IMAPS_2010 technical program page. This is the original abstract submitted by the author. Any changes to the technical content of the final manuscript published by IMAPS or the presentation that is given during the event is done by the author, not IMAPS.
|Advances in Wafer Level Processing and Integration for CIS Module Manufacturing|
|Keywords: CMOS image sensor, CIS module, Wafer level camera|
|Image sensors have become ubiquitous, appearing in cell-phone cameras, notebook webcams, digital cameras, video camcorders, security & surveillance systems, etc. Image sensors have come a long way since the first introduction of CCD sensor technology in the 1990's and made a big jump in the 2000's with the introduction of CIS technology. CIS gave birth to the low-cost, high volume camera phone market. Camera modules combine a CIS die with an optical system, a processor, and passives into a single package. The cost-effective integration of miniaturized cameras in mobile phones and other electronics is becoming realized through the introduction of CIS wafer level camera (WLC) module based on wafer-level processing and integration, which comprises wafer-level optics, backside illumination (BSI), WL-CSP, TSV interconnects, and heterogeneous integration with using Si interposer as major technical trends. In order to realize cost-effective camera module manufacturing, key enabling technologies based on wafer level processing are being developed and are paving the way to the future growth of digital imaging industry. Within EVG, various process developments were performed related to both the electrical and optical aspects of CIS modules, which include (a) lens molding at the wafer scale for both spherical and aspherical lenses, which can be molded on both sides of a wafer and the lenses are aligned/stacked to each other, (b) wafer and glass bonding based on thermo-compression, UV or fusion bonding techniques, (c) Cu TSV interconnects using NanoSpray coating technique for via-bottom opening, polymer insulation layer deposition, and conformal protection coating above Cu liner, (d) backend lithography for thick resist processing, forming Cu pillar, RDL and solder deposition, and (e) carrier technology based on temporary bonding and debonding for thin device wafer handling and processing. All technical trends and achievements related to those wafer-level processes will be presented at the conference.|
|Bioh Kim, Global Business Development Manager
EV Group, Inc.