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Wafer Level Assembly Technique Development for Fine Pitch Flip Chip 3D Die to Wafer Integration
Keywords: 3D Packaging, Die to Wafer Integration, Wafer Level Assembly
Three Dimensional (3D) Packaging has become an industry obsession as the market demand continues to grow for higher packaging densities and smaller form factor. In the mean time, wafer level packaging (WLP) is gaining popularity due to its high throughput and low cost per package. In this paper, a 3D Wafer Level Chip Scale Packaging (3D WLCSP) technology is introduced with emphasis on the development of the wafer level packaging assembly techniques. In this process, the Active Components, which is a fine pitch, thin profile flip chip, is face-to-face bonded to the PA (Passive Assembly) CSP carrier substrate on a 6-inch wafer that carries over 1,500 identical CSP substrates. A standard flip chip assembly process will be adopted for the assembly, in which the flip chips are picked, dip fluxed, and placed onto the CSP wafer. The wafer, once fully assembled with over 1,500 flip chips, will then be reflowed to form the solder joint interconnections in each individual package. After reflow, the packages will be underfilled by a capillary-based material and cured in the entire wafer format. Finally, the underfilled flip chip to WLCSP 3D package will be singulated using a dicing saw and packed for further second level assembly. Processing challenges addressed will include: · Machine vision recognition/alignment for fine pitch (85um) flip chip · High speed, high accuracy chip bonder programming on a wafer scale (how to place over 1,500 fine pitch flip chips onto the same wafer with high speed and high accuracy) · Reflow profile settings for the whole wafer · High throughput, high accuracy wafer level automated capillary underfill dispense methodology · The dicing process of a fully assembled wafer. The evaluation of the developed 3D Die to Wafer packaging processing technique will focus on the solder joint quality, intermetallic compound formation, package yield at the wafer level, and reliability performance of the singulated flip chip on CSP packages. The flip chip wafer level assembly technology explored in this paper will provide the industry a low cost, high throughput, high speed fine pitch flip chip 3D Die to Wafer integration solution.
Zhaozhi Li, Ph.D Candidate
Auburn University
Duluth, GA

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