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The Role of Wafer Bonding in 3D Integration and Packaging
Keywords: 3D Packaging, Wafer Level Bonding, Temporary Bonding
3D Integration and Packaging are currently described as “paradigm shifts”, “revolutionary technologies”, and other equally prophetic catch phrases. The realization of 3D to meet and exceed these expectations requires significant advances in surface preparation methods (CMP – chemical mechanical polishing), development of metal fill technologies (TSV – through silicon via etch, plating, and vapor deposition), redistribution layers, interposer technology, and micro bumping methods, advanced permanent bonding methods, thin wafer handling (materials, carriers, bonding and debonding), as well as simulators (architectural design to cost of ownership modeling). The complexity of 3D integration and packaging blurs the line between process node delineation and requires an overall evaluation and understanding of the entire process flows. All downstream processes are affected by the methods used prior to actual integration processing. Wafer level bonding is a key step, if not the fundamental step, in the success of 3D. If the stacking of the devices is not successful all the previous and subsequent steps are moot. The ultimate goal of 3D is the flow electrical signals between layers. This can be at the transistor level between memory layers as in 3D ICs, or it can be at the packaging level between the various heterogeneous devices e.g., logic controller to MEMS device. Permanent wafer bonding methods used in 3D involve metal bonding or hybrid approaches with metal and dielectric layers. The most often used materials are Cu and CuSn for 3D ICs and Au, Al, or Cu based eutectics for hermetic packaging and micro bumping. The process flows, requirements and specification requirements for each bonding technology are based on standard metrology metrics but the requirements for high yields are specific for each technology and will be discussed. Equally essential to the success of 3D integration and packaging, is the ability to retain final stack dimensions that meet the application form factor. For example, it would be unwise to promote vertically stacked devices that resulted in a “chip” that was several millimeter thick, when the applications require the devices to fit into smaller and smaller spaces. To facilitate stacking, minimize the vertical interconnect length, and achieve form factor requirements it is common to thin each layer in the stack to 50m or less. The development and fine turning of temporary adhesives, the support substrate options, and the quality of the debond and thin wafer transfer robustness are all advancing toward high volume manufacturing options. The leading technology choices for TWH with compatibility tables will be provided to assist in the selection process for various types of device applications.
Jim Hermanowski, Chief Scientist
SUSS MicroTec AG
Waterbury Center, VT
USA


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