Here is the abstract you requested from the IMAPS_2010 technical program page. This is the original abstract submitted by the author. Any changes to the technical content of the final manuscript published by IMAPS or the presentation that is given during the event is done by the author, not IMAPS.
|Ferro-Electrically Enhanced Proximity Communications: Microfabrication and Characterization|
|Keywords: packaging tolerances, chip I-O, ferroelectric materials|
|Capacitively-coupled communication between chips, commonly known as PxC, represents a new class of I-O signaling that offers substantially improved off-chip bandwidths. However, this form of communication presents a challenge from a packaging perspective, since tight chip alignment tolerances are required to maintain high signal fidelity and avoid cross coupling between neighboring channels. To mitigate the packaging constraints, capacitive coupling between the communication pads can be enhanced with materials that have high dielectric coefficients. Here, ferro-electrics hold promise over contemporary low and high K dielectrics, however their processing conditions need to be better understood and the compatibility with CMOS circuitry has to be established when integrated with a back end of the line process module. The issue for PxC is to align chips with sufficient accuracy to maintain high fidelity chip to chip signaling. One factor complicating signal integrity arises from the parasitics associated with the CMOS stack up that substantially reduce the chip coupling capacitance. As a result the chips relative alignment tolerances turn out to be about 1/3 the pad pitch while the interchip gap needs to be controlled well under ten microns. These alignment constraints are substantially smaller than contemporary, low-cost, pick and place tooling and chip gaps practiced within the area solder industry. One approach to mitigate the alignment challenge is to increase the dielectric coefficient between the chips and thereby alleviate the impact of the parasitic capacitance caused by the CMOS dielectric stack up. We report first on the simpler perovskite of Strontium Titanate (STO) and secondly Barium Strontium Titanate that were monolithically deposited at different temperatures atop Pt on Si. STO is paraelectric at room temperature and hence gigantic enhancements in dielectric coefficient are not expected. STO/BSTO were deposited using RF magnetron sputtering under different conditions. The obtained wafers were annealed at different temperatures using a thermal pulse under rapid thermal annealing. Devices were accomplished with variable upper electrodes (150nm Au on 9nm Ti) that were patterned onto the wafer using a lift-off step with NR-9 resist to form capacitive devices. The devices were then measured in a capacitance rig and fitted to area dependent geometry and frequency response algorithms. Enhanced capacitances of 500X greater than those in air have been measured. Integration to CMOS is reported as well as other application to SiPhontonics technology will be visited.|
|John E. Cunningham, Distinguish Engineer
Sun Labs at Oracle
San Diego, CA