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On the Origins, Status, and Future of FlipChip and Wafer Level Packaging
Keywords: WLCSP, Area Array Packaging, Wafer Level Packaging
As IC scaling continued to shrink transistors, the increased number of circuits per chip required more I/O per unit area (Rents rule). Eventually the ever increasing number of high I/O per die and the desire for consumer products to fit into ever smaller form factors drove the technological change towards die being interconnected (assembled) by area array techniques. This review will examine this evolution from die wire bonded on lead frames to flip chip die in wafer level or area array packages. Various options for UBM formation and solder deposition will be compared. Technologies for WLP will be contrasted and reliability of the various process options will be discussed. The move to copper pillar bumps will be examined. Fan out packaging, developed as a low cost option for increasing I/O per unit area will be examined and compared to fan-in techniques. 3-D packaging and system-in-package will be compared and contrasted to 3-D IC Integration and 3-D silicon interposers in terms of cost and performance benefits. The incorporation of passive integration into thin film bumping and redistribution technologies will be detailed.
Alan Huffman, Research Engineer
RTI International
Research Triangle Park, NC

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