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Reliability Testing for Microvias in Printed Wire Boards
Keywords: Microvias, PWB, PCB
Traditional single level microvia structures are generally considered the most robust level of interconnection in printed wire board (PWB) substrates. The rapid implementation of high density interconnect (HDI) now requires 2, 3 or 4 levels of microvias on either side of the substrate; these structures have proven less reliable. Recent false positive results from traditional thermal shock testing (cycling between -40C and 125C, or 145C) have resulted in a number of companies incurring the liability costs associated with replacing the circuit boards, components, and labour. This paper addresses new developments for establishing microvia interconnect reliability by means of more effective design and testing principles for thermal cycling of representative coupons. The paper includes the test methodology used for microvia structures with elevated test temperatures of 190C in FR4, and 230C in polyimide dielectric materials. The paper describes thermal cycling techniques of passive and passing low level current through the microvia test circuits. The reliability implications of various microvia configurations including stacked verse staggered, filled verse unfilled and microvias stacked onto internal buried vias will be reviewed. Concerns and considerations for microsection preparation, microvia evaluation and the anatomy of a robust microvia are presented. Six microvia failure modes are described.
Bill Birch,
PWB Interconnect Solutions Inc.
Nepean, Ontario K2H 9C1,

  • Amkor
  • ASE
  • Canon
  • Corning
  • EMD Performance Materials
  • Honeywell
  • Indium
  • Kester
  • Kyocera America
  • Master Bond
  • Micro Systems Technologies
  • MRSI
  • Palomar
  • Promex
  • Qualcomm
  • Quik-Pak
  • Raytheon
  • Specialty Coating Systems
  • Technic