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Embedded Power Packaging for Low Loss, High Performance
Keywords: power packaging, embedded chip, portable applications
Power electronics device packages must deliver power with minimal energy loss. and dissipate heat efficiently to minimize junction thermal rise. In the case power conversion for portable electronics, with low voltage, high current devices, input power and thermal management requirements can easily exceed the capabilities of conventional packaging approaches. Wire bonds with their high electrical parasitics limit device performance and have reliability issues associated with device microcracking. Flip chip solder bumps have severe thermal performance short comings and have reliability issues associated with CTE induced solder fatigue. New Embedded Power Packaging (EPP) technologies are emerging that increases power dissipation capabilities, dramatically reduces parasitic resistance and inductance in power devices while lowering junction to case thermal resistance. These technologies replace traditional wire bonds or emerging solder bumps with direct metallurgical electrical connections from the chip contact pads to the packages power busses. These structures can result in a 20% to 40% efficiency improvement. The planar structure also increases the achievable functional density and reduces the height profile allowing for enhanced design versatility and inherently lower inductance. Free of the performance limitations inherent with wire bond devices and thermal issues associated with flip chip devices, EPP technologies offer a solution to the challenges of packaging power. This paper presents EPP process, structure and materials from several different companies and reviews. A quantitative comparison will be presented of EPP electrical performance, thermal performance, manufacturability and cost with those of current power packaging alternatives.
Dr. Chuck Bauer, Senior Managing Director
TechLead Corporation
Portland, OR

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