Here is the abstract you requested from the MMC_2010 technical program page. This is the original abstract submitted by the author. Any changes to the technical content of the final manuscript published by IMAPS or the presentation that is given during the event is done by the author, not IMAPS.
|Hardware Design for a Ultra-High Processing Throughput Computer|
|Keywords: Meta-computer, ultra-high throughput, self-organizing|
|The objective of this research is to design a prototype of a multicellular metacomputer, containing over 4 million computing cells, and capable of running at 2 billion MIPS. The 4 million cells are packaged in an 8”x8”x8” space. The researched system is based on the interconnection of many very small computing cells. Each cell has multiple independent, high-speed, serial I/O channels, each operating at approximately 60 MHz. A cell has a five-bit word length and contains 32 words of Read Only Memory and 32 words of Random Access Memory as well as a set of internal five-bit registers. Each cell has its own internal clock. Each cell will therefore run at a slightly different speed as there is no synchronization between any of the cells. One serious problem facing massive arrangements of tiny computers is that the interconnections among the computers could occupy more space than the computers themselves. What if there is a way to arrange billions to trillions of computers in a cluster according to a design where there are virtually no wires among them. The multicellular metacomputer is designed to solve this problem.|