Here is the abstract you requested from the AIT_2011 technical program page. This is the original abstract submitted by the author. Any changes to the technical content of the final manuscript published by IMAPS or the presentation that is given during the event is done by the author, not IMAPS.
|Next Generation PoP Technology|
|Keywords: Advanced 3D packaging , Assembly and board level reliability , Package On Package (PoP)|
|Adoption of Package-On-Package (PoP) technology is becoming more widespread and is being mainly used in high-end Smartphone and other consumer electronics applications such as Mobile Internet Devices (MID) and tablets. PoP packages in production today have 0.50mm memory interface pitch (MIF) and 0.40mm bottom BGA pitch, and typically have the stacked height of 1.45mm max including the top memory package. In an effort to reduce the overall package height and maximize the allowable die size within the package, the next generation PoP in development today has a top MIF ball pitch of 0.40mm. This paper examines the performance of both bare die Flip Chip PoP (fcPoP) and Molded Laser Package PoP (MLP PoP) with 0.40mm MIF pitch in terms of the warpage, co-planarity, and assembly process challenges. In addition, Board Level Reliability (BLR) and Surface Mount Technology (SMT) of these package types are also reviewed. End of line high temperature warpage data and co-planarity results indicated that both package types are performing similarly with respect to these metrics, while resulting in the same package stack height. BLR evaluations done on MLP PoP version successfully passed JEDEC Drop Test requirements and completely passed 1000 cycles of BLR Temperature cycle test without any failures. Preliminary SMT evaluations performed on MLP PoP with sample size of 1000 units resulted in 99.8% SMT yield.|
|Hamid Eslampour , Deputy Director- Product & Technology Marketing