Abstract Preview

Here is the abstract you requested from the AIT_2011 technical program page. This is the original abstract submitted by the author. Any changes to the technical content of the final manuscript published by IMAPS or the presentation that is given during the event is done by the author, not IMAPS.

Reliability of 125um Flip Chip Interconnects for Wireless Applications
Keywords: reliability, 125um pitch flip chip, Cu pillar
Flip chip technology has seen tremendous growth since its first volume production more than 15 years ago. Flip chip has grown into a $16 billion market and accounted for about 13% of all IC packages in 2010. Flip chip is an attractive choice for the first level of interconnects due to its high packaging density, fine pitch scalability, improved electrical performance due to shorter electrical paths between the die and the substrate, better power ground distribution, etc. It has been reported that all new high end baseband processors used in mobile phones use flip chip, often within PoP package. This highly dynamic smart phone market introduces challenging requirements including shrinking form factors, smaller pitch, CMOS gate shrinking, higher power and interconnect density and improved reliability. With all the advances flip chip packaging technology has made in last decade, it is still considered to be in its growth phase and needs innovative solutions to address these fundamental challenges.
Rajesh Katkar, Sr. Manager Reliability and Failure Analysis
Invensas Corporation
San Jose, CA

  • Amkor
  • ASE
  • Canon
  • EMD Performance Materials
  • Honeywell
  • Indium
  • Kester
  • Kyocera America
  • Master Bond
  • Micro Systems Technologies
  • MRSI
  • Palomar
  • Plexus
  • Promex
  • Qualcomm
  • Quik-Pak
  • Raytheon
  • Specialty Coating Systems