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Effect of Abnormal Intermetallic Compounds Growth of Component Side on Board Level Mechanical Reliability
Keywords: Board level reliability, Pb-free solder, Intermetallic compounds
According to changing from leaded to lead-free solder by environmental regulation, unexpected problems have been often detected at lead free solder joint of board level package. For example, we experienced SnAgCu solder joint crack occurred clearly at IMC on component side, and all of solder joint in the one component had same crack mode. The root cause for this problem hasn't been defined yet. However, we suspected irregular IMCs of solder joint on component side came from abnormal reflow process and aging induced with bias voltage. In order to conduct experimental, we used component of board on chip (BOC) and FR4 PCB of unbuffered dual inline memory module (UDIMM) used in mass production of Samsung electronics. After reflow, (Cu,Ni)6Sn5 and (Ni,Cu)3Sn4 IMCs were observed at solder/UBM interface. With increasing of reflow times, thickness ratio of (Cu,Ni)6Sn5/(Ni,Cu)3Sn4 was changed from 12 to 4. Also, some voids were observed at interface between (Cu,Ni)6Sn5 and (Ni,Cu)3Sn4 due to effect of Ni, Cu and Sn diffusion difference during the liquid/solid reaction. However, in case of thermal aging, thickness of (Ni,Cu)3Sn4 IMC wasn't changed and any void wasn't observed at IMC interface. Also, for the IMC growth by solder reaction, the power law could be applied. Fitting the data for the IMC thickness to this equation, values of the power exponent were evaluated for reflow times and aging time, respectively. After all, 3 point bending test results were related to mechanical integrity of component side. In case of component increased reflow times, failure cycle has decreased obviously. However, component with increasing aging time did't affect on board level reliability. Therefore, we could get the results that void formation at interface between (Cu,Ni)6Sn5 and (Ni,Cu)3Sn4 on component side affected board level mechanical reliability, and suppression of void formed at (Cu,Ni)6Sn5/(Ni,Cu)3Sn4 interface will be proposed.
Jae-Hoon Choi, Senior Engineer
Samsung Electronics
Asan, Chung Nam 336-711,
Korea


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