Here is the abstract you requested from the DPC_2011 technical program page. This is the original abstract submitted by the author. Any changes to the technical content of the final manuscript published by IMAPS or the presentation that is given during the event is done by the author, not IMAPS.
|Cost Comparison of Fan-Out WLP vs. Embedded Die|
|Keywords: Cost Model, FOWLP, Embedded Die|
|Fabricating the package after the die is placed can result in smaller form factors, increased performance, and improved supply chain logistics for OEMs. There are many different approaches for this packaging technique, but two of the most prominent are Fan-Out WLP and Embedded Die. Fan-Out WLP leverages existing semiconductor technology for a cost effective approach to achieve relatively tight package design rules. The Embedded Die strategy leverages existing PCB lamination technology for cost-reduction through scale: fabricating many small packages on large production panels. We will examine the cost differences and similarities between Fan-Out WLP and Embedded Die strategies by developing a comprehensive cost model for each technology. We will then analyze the manufacturing costs (labor, material, depreciation, yield loss, and tooling) and yield impacts across a variety of designs to demonstrate the cost differences and similarities in each packaging technology.|
|Alan Palesko, Vice President
SavanSys Solutions LLC