Abstract Preview

Here is the abstract you requested from the DPC_2011 technical program page. This is the original abstract submitted by the author. Any changes to the technical content of the final manuscript published by IMAPS or the presentation that is given during the event is done by the author, not IMAPS.

Integrated Design and Full-Wave Analysis of Mixed Signal 3D Package Designs
Keywords: IC_package_combined_solvers, Mixed-Signal-Package, EDA_Flow
Design methodologies require thorough power and signal integrity analysis using full-wave (FW) three dimensional (3D) simulation technology. With RF and Analog content, design engineers need to simulate ICs in context of package parasitics. The ability to use a repeatable flow throughout the design cycle is a key requirement to meet tightly managed product schedules. This can be accomplished by an integrated flow that combines FW solver technology with IC/Package design, analysis and simulation flows. The single schematic driven IC and Package layout/solver flow allows simulation of mixed signal system across IC/Package with extracted parasitics. Such solution should allow a) Schematic driven object selection across IC/Package b) Auto-generation of package parasitic aware IC/Package-test benches c) Modeling of On-Chip / Off-Chip structures both in synthesis and analysis mode. The ability to merge IC and Package layout structures to allow FW extraction on combined 3D structure should be able to take different size structures and combined stack-ups. An automated flow for consuming extracted model for Signal and Power Integrity is also required to automate the process of connecting the model to the topology, especially when connections go up to 100s of IOs from package sub-circuit to IC-model sub-circuit. Finally an integrated FW-Solver to Layout is required. The designer should be able to make changes in the design and re-analyze without having to leave the design environment and move to solver tool-set. The paper explains the elements of the integrated flow as applied to GSM/EDGE Power amplifier design, composed of 3 dies on a laminate, electrically connected by wire bonds. The focus is to set on tolerances determined by the assembly in the production lines: 1) Chip/Die displacement, 2) Electrical connectivity of the chips to ground, 3) Bond-wire tolerances: height, length, drift, deformation. Complex multi-die package designs are able to be completed with significantly less time.
Antonio Ciccomancini Scogna,
San Mateio, CA

  • Amkor
  • ASE
  • Canon
  • EMD Performance Materials
  • Honeywell
  • Indium
  • Kester
  • Kyocera America
  • Master Bond
  • Micro Systems Technologies
  • MRSI
  • Palomar
  • Plexus
  • Promex
  • Qualcomm
  • Quik-Pak
  • Raytheon
  • Specialty Coating Systems