Here is the abstract you requested from the DPC_2011 technical program page. This is the original abstract submitted by the author. Any changes to the technical content of the final manuscript published by IMAPS or the presentation that is given during the event is done by the author, not IMAPS.
|Through-Sapphire Via Development|
|Keywords: sapphire, via, chip stacking|
|A sapphire wafer is insulative while a silicon wafer is semiconductor. Sapphire wafer presents different challenges and opportunities in the development of vias for chip stacking. Vias in sapphire can be used in wafer or die stacking for electronics densification and system size miniaturization. Results of an effort to realize vias in sapphire using laser will be presented. The metallization and filling process will be introduced. The data on filled via reliability and its analysis will be outlined. It is shown that clean vias can be realized. The vias can be filled void free. Filled via reliability data will be analyzed and discussed.|
|Syed Sajid Ahmad, Manager of Engineering Services
NDSU Center for Nanoscale Science and Engineering