Here is the abstract you requested from the DPC_2011 technical program page. This is the original abstract submitted by the author. Any changes to the technical content of the final manuscript published by IMAPS or the presentation that is given during the event is done by the author, not IMAPS.
|Novel Die-to-Wafer Interconnect Process for 3D-IC Utilizing a Thermo-Decomposable Adhesive and Cu-Cu Thermo-Compression Bonding|
|Keywords: Die-to-Wafer, 3D-IC, Bonding|
|Die-to-wafer interconnect offers key advantages for 3D-IC including heterogeneous die population using devices from different process lines, and higher yield by incorporating only known-good die. Attaching the dies to a wafer, however, typically involves serial processing whereby each die is aligned and bonded one at a time. This can be prohibitively time consuming particularly when using a slow, high-temperature process such as Cu-Cu thermo-compression for each die in succession. Also, the high temperatures applied locally can adversely affect neighboring sites by oxidizing the Cu bonding surface if not protected in an oxygen-free environment. We have developed a novel die-to-wafer interconnect process that circumvents these problems using a die-tacking and global-bonding approach. Using a high-accuracy die placement tool, individual dies are aligned and tacked onto a wafer that is coated with a thermo-decomposable adhesive layer. The low-temperature tacking process avoids oxidation of the Cu bonding surfaces, minimizes thermal cycling, and increases throughput significantly. Once the wafer is fully populated, it is then processed in a closed-chamber wafer-bonding tool, which provides an oxygen-free environment. All of the dies are bonded in parallel using a high-temperature Cu-Cu bonding process to globally apply the required heat and force. Once the adhesive is heated past its critical decomposition temperature, it cleanly vaporizes away and allows the Cu-Cu bonding to proceed. We have successfully demonstrated this process on a 300mm platform using custom-designed test dies and wafers containing through-silicon via (TSV) chains and Kelvin test structures providing 4-point resistance measurements. Experimental results including TSV chain yield, electrical resistance, alignment accuracy, and cross-sectional analysis will be presented. A discussion will also be given on the potential cost savings and future technical challenges of this approach.|
|Daniel N. Pascual,