Here is the abstract you requested from the DPC_2011 technical program page. This is the original abstract submitted by the author. Any changes to the technical content of the final manuscript published by IMAPS or the presentation that is given during the event is done by the author, not IMAPS.
|Z-Axis Interconnection in Organic Packaging|
|Keywords: organic packaging, multi-chip module, z-axis interconnect|
|Greater I/O density at the die level, more demanding performance requirements, and the continued desire to package more function into smaller devices is driving the need for improved wiring density and a concomitant reduction in feature sizes for electronic packages. Traditionally, greater wiring densities have been achieved by reducing the dimensions of vias, lines, and spaces, while also increasing the number of wiring layers. However, each of these methods possesses inherent limitations in today's most challenging multi-chip module (MCM) and system-in-package (SiP) applications that also demand reduction in size, weight and power (SWaP). These applications are forcing new methods to be developed for achieving greater wiring densities while also meeting the cost for performance challenges that exist within this industry. One method of extending wiring density beyond the limits imposed by today's traditional approaches is the strategy of making metal-to-metal z-axis interconnection of subcomposites during lamination to form a composite structure. Conductive joints can be formed during lamination using an electrically conductive paste. As a result, one is able to fabricate structures with vertically-terminated vias of arbitrary depth. Replacement of conventional plated through holes with vertically-terminated vias opens up additional wiring channels on layers above and below the terminated vias, enables die shrink, and eliminates via stubs which cause reflective signal loss. In addition, parallel lamination of individually testable subcomposites offers opportunity for yield improvement, shorter cycle times, and ease of incorporating embedded features conducive to SiP applications. This technique has also been shown to be viable across a multitude of dielectric material sets (including Teflon, PPE, LCP and Epoxies) as well as various conductive joining materials allowing it to be utilized in various applications as well as giving designers the flexibility to mix materials within the same package to incorporate various functionality.|
|Frank Egitto, Senior Advisory Technologist
Endicott Interconnect Technologies