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Failure Analysis and Reliability of 3D Integrated System
Keywords: TSV technology, 3D integrated systems, Reliability
Today 3D integration based on through silicon vias (TSV) is a well-accepted approach to overcome the performance bottleneck and simultaneously shrink the form factor. According to the ITRS road map [1] there is a variety of reasons for application of 3D integration, such as miniaturization, improved circuit performance, lower power consumption and heterogeneous integration. World-wide, several full 3D process flows have been demonstrated. However, there is a strong demand for considering the behaviour and reliability of 3D-integrated systems [2]. Explicitly, the impact of 3D processes on the system, e.g. thermo-mechanical stresses, has to be evaluated before the implementation to production lines. A test chip for reliability evaluation of 3D TSV technologies was designed and fabricated by Fraunhofer EMFT. The 3D-integrated reliability test chip is a 3-level-stack with TSVs through a middle (2nd) device layer to connect structures on the bottom (1st) level with the top (3rd) level device. The layout is modular, so you can test basic assembly processing with the combination of level 1 with level 2 only and the influence of additional processing when adding level 3. For reliability testing, temperature cycling following the JEDEC standard was performed from -55 C° to +150 °C (at a soak time of 5 minutes). Additionally, analysis was done by cross sectioning and reversed engineering. The 3D-integrated test chips were fabricated by application of Fraunhofer EMFT´s TSV SLID technology. The applied 3D TSV process is based on intermetallic compound (IMC) bonding and TSV formation before stacking [3]. Reliability issues related to thermo-mechanical stress caused by the 3D integration process have to be considered. Failures of 3D integrated systems caused by TSV formation and the permanent bonding process were analysed by a novel high rate milling Focussed Ion Beam equipment. Figure 1 schematically shows the application of the novel FIB analysis technique for the areas of interest (IMC bond, TSV cross sections). Compared to classical FIB systems, the new equipment allows to remove material significantly faster while maintaining good resolution at low beam currents, important for the subsequent analysis. Cross sections of the 3-layer stack are shown in Figure 2. The merits of the novel plasma FIB and the resulting failure analysis will be discussed in detail. References [1] Semiconductor Industry Association, “The International Technology Roadmap for Semiconductors”, 2009 Edition. SEMATECH:Austin, TX, 2009 [2] P. Ramm, J. Wolf, B. Wunderle, “Wafer-Level 3D System Integration” in Handbook of 3D Integration, edited by Philip Garrou, Chris Bower, Peter Ramm, Wiley-VCH, 2008 (ISBN: 978-3-527-32034-9) [3] P. Ramm, A. Klumpp, J. Weber, “3D Integration Technologies for MEMS/IC Systems”, Proc. IEEE Bipolar / BiCMOS Circuits and Technology Meeting, Capri – BCTM 2009, p. 138 Figure 1: Schematic cross section of the 3-layer reliability test chip and application of the novel FIB analysis technique. Figure 2: Cross sections of the 3-layer stack test chip, showing TSV and IMC bond pads
Peter Ramm, Head of Department
Fraunhofer EMFT
Munich 80686,

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