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3D-TSV Test Options and Process Compatibility
Keywords: 3D-TSV, probing, KGD
3D-TSV stacking with non-reworkable bonding processes implies known-good die screening with high test coverage to be economical. • Depending upon the stack architecture, the need to contact TSVs directly or TSV bonding pads during wafer test ranges from minimal to mandatory. An example of minimal need to contact is a low-power logic or memory chip powered and tested through a small number of test pads for scan chains or built-in self-test (BIST) signals. Examples of mandatory TSV pad contact during wafer test include power delivery pins (up to thousands), analog or RF I/Os, stacked logic functions, or more complex requirements. • With appropriate design, test throughput (and therefore test cost) can dramatically benefit from contacting the many more I/Os available at the TSVs or TSV pads, just as the speed of the stack benefits from the many more I/Os when in mission mode. • Probes and probing processes that touch TSVs and thin pads with minimal forces and pad marking are described herein. Feasibility of tip forces ~1 gram or less and very low pad damage are demonstrated at 40 micron array pitch. The lithographically printed probe structures are scalable to even smaller pitches, and fabrication costs scale by probe area, not by pincount. • The degree of pad marking from probe tips depends on pad material choices. A non-oxidizing metal surface, such as ENIG, requires <0.1 gm for good contact, thus disturbing the surface so little that marks are difficult to detect. By contrast, a Sn surface requires ~1 gm for low and consistent contact resistance. Probe contacting at TSV pitches is practical with evolutions of existing probe technology, and enables test strategies which probe some or all of the TSV pads, whether on the face or back of the wafer.
Ken Smith, Principal Engineer
Cascade Microtech, Inc.
Beaverton, OR
USA


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