Micross

Abstract Preview

Here is the abstract you requested from the DPC_2011 technical program page. This is the original abstract submitted by the author. Any changes to the technical content of the final manuscript published by IMAPS or the presentation that is given during the event is done by the author, not IMAPS.

Packaging Related Failure Modes of Microelectronic Components
Keywords: failure analysis, warpage, package
Today's electronics development is governed by two trends: miniaturization of size and increase of power, which both contribute to significantly higher operation temperatures of the components and assemblies. Additionally, with the establishment of the RoHS standards, also the assembly process takes place at temperatures which are significantly higher than some few years ago. Therefore the package needs to protect the component against higher and higher temperatures during the entire component live time, from assembly through the entire operation cycle. The packaging design engineer disposes of a large number of parameters to optimize each packaging for its individual application. Even in the “simple” case of just a small silicon die in a small package, the specific composition of the mould compound may make the difference between an “easy-to-solder” package and one with repetitive failure issues during soldering and/or product operation. It is immediately clear that the situation is even much more complicated in case of highly evolved MEMS components. Modern type cavity based sensor packages need to be designed for minimum component warpage during the entire product live time, a task which is particularly challenging for the 260°C top temperature the component may face during assembly. In the present paper we will apply our TDM (Topography and Deformation Measurement) system to monitor the warpage behavior of various components during temperature cycles which are either typical for the solder process, or for the components operation conditions. Simultaneously with heating or cooling the components, high resolution (µm range) topographies will be obtained on the components packaging. These topography and deformation maps will be used to analyze potential packaging related failure modes. An example will be presented how to optimize a MEMS packaging process only by carefully adjusting the assembly conditions, without any variation of the packaging materials or design.
Michael Hertl, CTO
Insidix
Seyssins 38180,
France


CORPORATE PREMIER MEMBERS
  • Amkor
  • ASE
  • Canon
  • EMD Performance Materials
  • Honeywell
  • Indium
  • Kester
  • Kyocera America
  • Master Bond
  • Micro Systems Technologies
  • MRSI
  • NGK NTK
  • Palomar
  • Plexus
  • Promex
  • Qualcomm
  • Quik-Pak
  • Raytheon
  • Specialty Coating Systems