Here is the abstract you requested from the DPC_2011 technical program page. This is the original abstract submitted by the author. Any changes to the technical content of the final manuscript published by IMAPS or the presentation that is given during the event is done by the author, not IMAPS.
|Flip Chip Fine Pitch PBGA Yield Study|
|Keywords: Flip Chip Yield Simulation, Fine pitch, Substrate warpage|
|With demands for higher electrical performance of Flip Chip Devices, the combined effect of fine bump pitch and thinner substrates impacts the die to substrate bump interface yield at assembly. This study utilizes Surface Evolver and Monte Carlo simulations to study the effects of bump design, warpage, and die size on bump yield loss. While warpage at solidification temperature proves to be the largest contributor to bump yield loss, there are design parameters that can be adjusted to maximize yield at various warpage and die size profiles.|
|Tim Pham, Flip Chip Integration