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A Novel Approach to 3D Chip Stacking
Keywords: 3D, die-stacking, SiP
Designers seeking electronic package miniaturization but lacking the resources to utilize custom ASIC or complex 3D integration approaches can now take advantage of chip stacking technology for integrating a range of devices into small, system-in-package (SiP) structures. A robust, innovative approach, suitable for supporting low- to medium-volume applications, has been developed which avoids the cost and/or size penalties typically encountered using traditional multi-chip packaging techniques. Using bare die and vertical interconnect/interposer structures, this stacking technology permits the design of multi-chip assemblies with either identical or dissimilar die, co-packaged with discrete and/or integrated passive devices. The approach is independent of ASIC foundry process and does not require through-silicon via (TSV) technology, and is therefore well-suited for designs incorporating multiple IC's from different semiconductor processes or manufacturing sources. Relative to system-on-chip (SoC) ASIC implementations, which carry large upfront NRE costs and long development cycles, 3D co-packaging of heterogeneous devices in customized SiP packages offers a proven, cost-effective alternative with greater design flexibility and reduced time to market. This presentation will describe this novel 3D packaging approach, and how it can be used in conjunction with discrete and integrated passive components to address package designs where size, weight, and/or performance are at a premium.
Mark Vandermeulen, Program Manager
ON Semiconductor
Burlington, ON L7L 5P5,

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