Abstract Preview

Here is the abstract you requested from the DPC_2011 technical program page. This is the original abstract submitted by the author. Any changes to the technical content of the final manuscript published by IMAPS or the presentation that is given during the event is done by the author, not IMAPS.

Low Profile 3D-IPD for Advanced Wafer Level Packaging
Keywords: IPD, 3D, WLP
Thanks to their 3D structure, the Silicon Capacitors offer drastic improvements in terms of performances compared to the commonly used ceramic and tantalum capacitors. They are also a smart way to reduce the application volume and increase the IP protection level. With the increasing complexity in the die and package designs and ever increasing cost pressure in today's microelectronic industry, IPDIA is offering for a large range of products, customized or standard components, a low cost packaging solution: the Wafer Level Chip Scale Packaging. While wire-bond interface may remain the preference for many applications, face-down direct chip attachment has gained wide acceptance. More than interacting on electrical functionality, WLCSP is interacting on mechanical and thermo mechanical properties with a higher miniaturization and a transfer directly on printed circuit boards without additional packaging steps. This paper presents the main characteristics of the 3D-IPD advanced technology emphasizing on its capability and advantages versus discrete components illustrated by different applications using ultra-thin IPD ( down to 60µm ) and WLCSP.
Catherine Bunel, R&D Director
CAEN, Calvados 14000,

  • Amkor
  • ASE
  • Canon
  • Corning
  • EMD Performance Materials
  • Honeywell
  • Indium
  • Kester
  • Kyocera America
  • Master Bond
  • Micro Systems Technologies
  • MRSI
  • Palomar
  • Promex
  • Qualcomm
  • Quik-Pak
  • Raytheon
  • Specialty Coating Systems
  • Technic